Embedded Systems and Computer Architecture – Department of Computer Engineering http://www.ce.pdn.ac.lk University of Peradeniya Sun, 21 Jul 2019 02:34:20 +0000 en-US hourly 1 https://wordpress.org/?v=5.2.1 https://cepdnaclk.github.io/department-website-2021/wp-content/uploads/2019/05/cropped-University_of_Peradeniya_crest-32x32.png Embedded Systems and Computer Architecture – Department of Computer Engineering http://www.ce.pdn.ac.lk 32 32 Implementing an Affordable Environmental Monitoring and ControllingSystem (EMCS) for Greenhouse. https://cepdnaclk.github.io/department-website-2021/project/implementing-an-affordable-environmental-monitoring-and-controllingsystem-emcs-for-greenhouse/ Fri, 07 Jun 2019 09:02:53 +0000 http://192.248.42.20/?post_type=post-k-project&p=392860 Team Members
    • Lashan Faliq
    • Himasha De silva
    • Dinuka Nadeeshan
Traditional farming methods are becoming ineffective due to the increase of population and reducing land for cultivation. Therefore precision agriculture or more precisely greenhouses are important in this day and age also to get the maximum precision in the controlled environment we discussed the importance of a controlling and monitoring system to be in effect. Further, we discussed why a Wireless Sensor Network or WSN was used and which WSN is most suited to a monitoring and control system. Further, it was discussed about most of the frequently used sensors and the system architectures used in most of the papers and how our architecture is similar or different from those. Then we discussed the uses of self-learning and image processing in the field of precision agriculture and how our project uses a deep learning model to control the actuators. Finally, we are using an image processing model to identify optimal conditions of specific plants in a Controlled Environment.
]]> Low Power Hardware Trojan Detection, Identification, and Recovery Mechanism https://cepdnaclk.github.io/department-website-2021/project/low-power-hardware-trojan-detection-identification-and-recovery-mechanism/ Fri, 07 Jun 2019 06:40:29 +0000 http://192.248.42.20/?post_type=post-k-project&p=392766 Team Members
    • Kisaru Liyanage
    • Chathura Nagoda Gamage
The security and reliability of an Integrated Circuit (IC) are challenged by the possibility of hardware Trojans being inserted into it during its development process. A malicious third party who involves in any phase of IC development process could inject a hardware Trojan to make the circuit deviate from its intended function or leak sensitive data processed by the circuit. Many prevention mechanisms and countermeasures have been proposed to overcome the hardware Trojans due to the adverse effects of them on crucial systems. In this paper, we discuss the state-of-the-art Triple Modular Redundancy (TMR) based hardware Trojan detection, identification, and recovery mechanism. Then we present a novel mechanism based on Dual Modular Redundancy (DMR) to improve the dynamic power consumption of the TMR mechanism. Moreover, we implement an automation framework to generate the above secure systems in less than 50 milliseconds. Finally, we evaluate the generated secure systems using a standard benchmark, AES.
]]> Application of Swarm Intelligence in Multi-Robot Systems https://cepdnaclk.github.io/department-website-2021/project/application-of-swarm-intelligence-in-multi-robot-systems/ Fri, 07 Jun 2019 06:28:27 +0000 http://192.248.42.20/?post_type=post-k-project&p=392760 Team Members
    • Kaushal Amarasinghe
    • Shashika Chathuranga
    • Milinda Sandaruwan
This paper is about the Swarm Robotics research that is still going on. First, an introduction into the Swarm Robotics and Swarm Intelligence is given and the current status of the research that is found in the field of Swarm Robotics is explained. Moreover, related work in the field of Swarm Robotics is also discussed. Then, problems that are found and our approach to solve a few of those problems are discussed. Next, the methodology that was used and a few experiments that were done are explained. Thereafter, it contains the results analysis and the findings of this project. Finally, the conclusions and future work are discussed. Swarm Robotics is basically a swarm of robots working together collaboratively to perform a simple task. Swarm Intelligence is one of the main techniques used in Swarm Robotics. Swarm Intelligence is seemingly unintelligent robot units working together to achieve a common goal in a way that it appears they have an intelligence of their own. Applying Swarm Intelligence into a robot system gave the rise to the idea of Swarm Robotics. There are many use cases for swarm robotics ranging from education robots to life rescuing robots in cases of emergency.There are even swarms of robots in the air too
]]> Power Aware High-Level Synthesis Flow for Mapping Large-Scale FPGA Designs https://cepdnaclk.github.io/department-website-2021/2019/06/07/power-aware-high-level-synthesis-flow-for-mapping-large-scale-fpga-designs/ Fri, 07 Jun 2019 06:05:35 +0000 http://192.248.42.20/?post_type=post-k-project&p=392751 ]]> Team Members
      • Udaree Kanewala
      • Kesara Gamlath
      • Hasindu Ramanayake
      • Kalindu Herath
Present Field Programmable Gate Array (FPGA) manufacturers incorporate multi-millions of logic resources which enables hardware designers to design applications extend ing to enormous scales. However, handling such applications by existing FPGA Computer Aided Design (CAD) flow requires more improvement in terms of compilation time, performance and power efficiency considerations. However, the existing CAD flow requires the input design to be in Register Transfer Level (RTL). This limits the design productivity only to hardware experts in performing analysis for optimizations on large-scale designs. Optimizing larger RTL designs manually is increasingly difficult. High-Level Synthesis (HLS) is an approach capable of increasing the design productivity of hardware applications compared to commonly used Hardware Description Languages (HDLs) and is known to be a capable approach for performing optimizations at a higher level of abstraction. Our concern is to propose an approach that follows the HLS flow to cater the mapping of large scale applications to FPGA in a power efficient manner. From our experiments, it was possible to achieve an average reduction of 6.7% routing thermal power and 2.42% total power.
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