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RV32IM Network on Chip Design and Implementation


Table of Contents

  1. Introduction
  2. Pipeline Datapath
  3. Team
  4. Supervisors
  5. Links

Introduction

Under extended features we designed a Network of Chip to interconnect 16 RV32IM CPU instances using a mesh network. Mesh network is used by the CPU instances to communicate with other CPU instances and to access the main memory through the memory controllers. Figure 1 shows the basic design of the NoC.

As shown in Figure 1, the main hardware components of the NoC,

  • Nodes
  • Routers
  • Main memory
  • Memory Controller

GitHub Repository


Overview of the Network on Chip

Overview


Team

  • E/16/069, Damsy De Silve, email
  • E/16/094, Shirly Ekanayake, email
  • E/16/276, Buddhi Perera, email

Supervisors

  • Dr. Isuru Navinna
  • Dr. Mahanama Wickramasinghe