RV32IM Pipeline Implementation - Group 1


Table of Contents

  1. Introduction
  2. Pipeline Datapath
  3. Hardware Units
  4. Links


This project aims to implement an in-order 5-stage pipelined CPU which implements the RV32I base instruction set and the M instruction set extension for multiplication/division operations as per the RISC-V ISA specification.

Pipeline Datapath

The CPU design consists of the following stages.

The pipeline datapath for the CPU is illustrated in the following diagram along with the labeled data and control signal.

Pipeline Datapath

Hardware Units

Within the design, the following primary hardware units can be identified.