The Objective of this Project

The project aims to create a Central Processing Unit (CPU) with a 5-stage pipeline to support the RISC-V instruction architecture. The CPU is designed to specifically support the entire RV32IM ISA. The implementation of the pipeline CPU is achieved through behavioral modeling in verilogHDL, which is a hardware description language used to describe digital circuits. The icarus Verilog compiler and simulator are used to compile and simulate the design, while gtkWave is used to observe and analyze the behavior of the CPU during simulation. Overall, the project seeks to create an efficient and effective CPU design that can execute the RISC-V instruction set accurately and quickly.

The RISC-V Architecture

An open-source Instruction Set Architecture (ISA) designed for use in computer processors. It is based on the Reduced Instruction Set Computer (RISC) principles, which emphasize simple, efficient, and standardized instructions that can be executed quickly.

The RISC-V architecture is modular, which means that it can be customized for specific applications and requirements. It supports both 32-bit and 64-bit processing, and it includes a range of extensions that provide additional features and functionality. Some of the extensions available for the RISC-V architecture include:

  • F (Floating-Point): adds support for floating-point operations.
  • D (Double-Precision Floating-Point): adds support for double-precision floating-point operations.
  • A (Atomic): adds support for atomic memory operations.
  • M (Integer Multiplication and Division): adds hardware support for integer multiplication and division.
  • C (Compressed): reduces the size of instructions by encoding some instructions in a smaller format.

One of the key advantages of the RISC-V architecture is its open-source nature. This means that anyone can use, modify, and distribute the architecture without needing to pay licensing fees or obtain permission from a specific company. This has led to a growing ecosystem of hardware and software developers who are building products and tools around the RISC-V architecture.

Phase 1 (Planning)

During the first phase of our project, we completed two main activities: describing the instructions and creating a pipeline diagram with datapath and control.

Activity 1

For Activity 1, we thoroughly examined the RISC-V instruction set architecture to gain a clear understanding of the instructions and their usage. Additionally, we carefully identified the instruction encoding formats, including the fields and positions within each instruction encoding, and clearly labeled the unique opcodes that correspond to each instruction. This information is critical in ensuring the accurate execution of programs on the CPU.

Activity 2

For Activity 2, we created a pipeline diagram with datapath and control to visualize the hardware units and signals involved in the CPU design. We identified and labeled each hardware unit involved in the pipeline, such as the ALU, register file, and memory unit. In addition, we carefully identified and labeled the signals used to transfer data between the hardware units and control the flow of data through the pipeline. This allowed us to clearly understand the flow of data and control through the CPU design, ensuring that it is efficient and effective in executing instructions.

Document Pipeline Diagram

We will be open to making modifications to the initial design of the CPU in the planning phase of the project based on sound reasoning and evidence. We will continue to evaluate the effectiveness and accuracy of the CPU design as the project progresses and make necessary modifications. The ultimate goal is to create a high-quality CPU that efficiently and accurately executes the RV32IM.

Phase 2 (Hardware Units)

During the second phase of our project, we started the implementation with building Integer ALU, Register File, Control Unit and other data-path elements as well.

To implement our design, we started by building the following datapath elements: an Integer Arithmetic Logic Unit (ALU), a Register File, and a Control Unit. The ALU is responsible for performing arithmetic and logical operations. The Register File contains a set of registers that can be read from or written to by the ALU and other datapath elements. The Control Unit generates control signals that coordinate the operations of the datapath elements.

While implementing our design, we also considered building other datapath elements as needed to ensure the overall functionality of the system. By developing these elements in a systematic and coordinated manner, we aim to create a reliable and efficient datapath that meets our design specifications.

Document Pipeline Diagram

Phase 3 (Integration)

During the third phase of our project, we integrated our pipelined processor, which includes datapath, control, instruction/data memory, caching, assembler, and test programs.

The pipelined processor is a sophisticated computer architecture that integrates various components to achieve efficient processing of data and instructions. At its core lies the datapath, which handles the execution of instructions by performing arithmetic and logical operations on data stored in registers. The datapath is driven by the control unit, which generates control signals based on the current instruction being executed.

To enhance performance, the pipelined processor includes instruction and data memory, along with caching mechanisms that help reduce memory access latency. The processor also incorporates an assembler, which translates assembly code into machine code, allowing the processor to execute instructions.

To ensure proper functioning of the pipelined processor, a suite of test programs have been developed to thoroughly test the system's functionality and performance. By integrating all of these components, the pipelined processor provides a powerful platform for efficient execution of programs and processing of data.

Document Pipeline Diagram

Phase 4 (Hazard Handling)

During the fourth phase of our project, we handled hazards in our pipelined processor, which includes datapath, control, instruction/data memory, caching, assembler, and test programs.

Hazard handling is a crucial aspect of computer architecture, especially in modern processor designs like RISC-V. In the context of RISC-V, hazard handling refers to the techniques and mechanisms employed to address potential issues that arise due to dependencies and timing conflicts among instructions. hese hazards can impact the proper execution and performance of a processor.

This simplicity can lead to hazards that need to be managed effectively. Hazards can occur in different forms, such as data hazards, control hazards, and structural hazards. Data hazards occur when there are dependencies between instructions, and the availability of data for one instruction is dependent on the completion of another instruction. This can lead to incorrect results or delays in execution. Control hazards arise when the control flow of instructions is affected, such as branching or jumping to a different instruction address. This project is only focused on Data hazards and Control hazards.

To handle these hazards, RISC-V employs various techniques. One commonly used technique is instruction forwarding, which allows the result of a previous instruction to be directly forwarded to a dependent instruction, eliminating the need to wait for it to be written back to the register file. Branch prediction is another important technique used to mitigate control hazards by predicting the outcome of a branch instruction and speculatively executing instructions based on that prediction.

Document Pipeline Diagram

Our Team

Nipun Dharmarathne


Shamod Wijerathne


Chathura Wimalasiri



Dr. Isuru Nawinne

Dr. Mahanama Wickramasinghe