Designing a RISC-V Based ASIP for Accelerating Third-Generation DNA Sequence Alignment on Embedded Systems

Team

Supervisors

Table of content

  1. Abstract
  2. Related works
  3. Methodology
  4. Experiment Setup and Implementation
  5. Results and Analysis
  6. Conclusion
  7. Publications
  8. Links

Abstract

This project explores the design and implementation of a RISC-V-based Application-Specific Instruction-set Processor (ASIP) to accelerate DNA sequence alignment for embedded systems. By focusing on the computationally intensive chaining stage of Minimap2, the project aims to achieve real-time, energy-efficient processing for third-generation DNA sequencing technologies.


The project builds upon existing research in DNA sequence alignment, hardware acceleration, and RISC-V-based processor design. Key references include:


Methodology

  1. Performance Analysis: Profiling Minimap2 to identify bottlenecks in the chaining stage.
  2. ASIP Design: Developing a custom co-processor using the RISC-V Rocket Chip platform and RoCC interface.
  3. Simulation and Testing: Verifying the ASIP design using simulation tools and benchmarking its performance.
  4. Integration: Incorporating the ASIP into an embedded system for real-world testing.

Experiment Setup and Implementation


Results and Analysis


Conclusion

The project successfully demonstrates the feasibility of using a RISC-V-based ASIP to accelerate DNA sequence alignment on embedded systems. Future work includes extending the design to other stages of Minimap2 and deploying the solution on FPGA for real-world applications.


Publications