RV32IM Pipeline Implementation Group1

Team

Supervisors

Table of Contents

  1. Introduction
  2. Processor Design
  3. Implementation Details
  4. Links

Introduction

This project implements a RISC-V RV32IM processor using a 6-stage pipeline architecture to improve performance and efficiency. The processor supports integer arithmetic, multiplication, and memory operations as defined in the RV32IM instruction set. Designed for FPGA deployment, this implementation optimizes execution speed and minimizes stalls using pipeline forwarding and hazard detection techniques.

The project aims to provide a fully functional, verifiable processor with an open-source implementation, useful for academic research and practical FPGA-based applications.

Processor Design

The processor follows a 6-stage pipeline structure:

  1. Instruction Fetch (IF) – Fetches instructions from memory.
  2. Instruction Decode (ID) – Decodes instruction and reads registers.
  3. Execute (EX) – Performs arithmetic and logic operations.
  4. Memory Access (MEM) – Handles load/store operations.
  5. Write-Back (WB) – Writes results back to registers.
  6. Hazard Handling & Forwarding (HF) – Implements data forwarding and hazard mitigation.

Implementation Details