CO502: Advanced Computer Architecture
| Course Number : CO502 | ||||||
|---|---|---|---|---|---|---|
| Course Title : Discrete Mathematics | ||||||
| Credits : 3 | ||||||
| Prerequisites : CO213 Computer Architecture | ||||||
| No | Course Content | Time Allocated (hours) | ||||
| L | T | P | A | |||
| 01 | Fundamentals of Computer Design Technology, cost and price and their trends. Measuring and reporting performance. Quantitative principles of computer design. Instruction set architecture and principles. Memory addressing and addressing modes. |
2 |
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| 02 | Introduction to Instruction Level Parallelism (ILP) Concepts and challenges of instruction level parallelism. Overcoming dependency boundaries with dynamic scheduling. Introduction to multiple issue processors. Performance improvement of multi-issue processors with instruction level parallelism. Thread level parallelism. |
3 | 1 |
1 | ||
| 03 | Pipelined Processors Pipelining hazards. Handling hazards with software scheduling. Hardware design approaches to manage hazards: hardware stalls, forwarding and delayed branching. Pipelining and current microprocessor. |
2 | 1 | 1 | 1 | |
| 04 | Exploiting ILP with Software Approaches Exposing instruction level parallelism with compiler techniques. Static branch prediction. Static multi issues: the very long instruction word (VLIW) architecture. Hardware and software speculation mechanisms. Instruction level parallelism in the embedded and mobile processors. |
4 | 2 | 2 | 2 | |
| 05 | Exploiting ILP with Hardware Approaches Dynamic scheduling and superscalar processors. Hardware based speculation. Dynamic branch prediction. In order verses out of order execution. Limitations of instruction level parallelism in practical processor design. |
3 | 1 | 2 | 4 | |
| 06 | Memory Hierarchy Design Review of caches. Improving performance of caches: Reducing miss penalty/rates and hit time. Reducing cache miss penalty and miss rate via parallelism. Virtual memory protection. Shared-memory architectures: symmetric and distributed. Performance of shared-memory architectures. |
3 | 4 | |||
| 07 | Hardware Description Languages and Simulation Using a hardware description language (HDL) to model a single scalar RISC processor. Introduction to hardware simulators. Hardware testing and verification using HDL simulation tools. |
1 | 1 | 8 |
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| 08 | Computer Architecture and Dependability Reliability, availability and dependability issues in computer systems. Special hardware features to enable reliability and security of microprocessors. |
4 |
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2 | ||
| 09 | Special Purpose Processors Low power design methodologies. Processor customization based on applications: Application specific integrated circuits (ASIC), Application Specific Processors and Field programmable gate arrays (FPGA). |
3 | 2 | |||
| Total | 25 | 5 | 14 | 16 | ||
| Assessment | Percentage Marks | |||||
| Continuous Assessment | 50 | |||||
| Tutorials / Labs | 10 | |||||
| Assignments / Projects | 40 | |||||
| Written Examinations | 50 | |||||
| Mid-Semester | 20 | |||||
| End of Semester | 30 | |||||