RV32IM Pipeline Implementation

Table of Contents

  1. Introduction
  2. Pipeline Datapath
  3. Hardware Units
  4. Team
  5. Supervisors
  6. Links


The aim of this project is to design and implement a pipelined processor which supports RISC-V Instruction Set Architecture. VerilogHDL and Icarus verilog is used to implement this CPU. Gtkwave is used to observe the behaviour of the CPU.

Pipeline Datapath

Instruction Memory

responsible for storing program instructions that the CPU will execute.The program counter (PC) holds the address of the next instruction to be fetched from the Instruction Memory

Data Memory

responsible for storing data that the CPU uses and manipulates during program execution.During program execution, the CPU may read data from the Data Memory or write data to the Data Memory.

Cache Memory

stores frequently used data and instructions to improve the performance.

Register File

Control Unit

manages and coordinates the operations of the other hardware units, and directs the flow of data through the datapath to execute instructions

Pipeline Registers

temporarily store data between stages of the pipeline


Hardware Units