Project Title

RV32MI pipeline Implementation —

Team

• E/20/419 - Wakkumbura M.M.S.S. (e20419@eng.pdn.ac.lk)
• E/20/439 - Wickramasinghe J.M.W.G.R.L. (e20439@eng.pdn.ac.lk)
• E/20/036 - Bandara K.G.R.I (e20036@eng.pdn.ac.lk)

Supervisors

• Dr. Isuru Nawinne (isurunawinne@eng.pdn.ac.lk)

Table of Contents

1. Introduction
2. Other Sub Topics
3. Links

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Introduction

This project aims to implement an in-order 5-stage pipelined CPU which implements the RV32I base instruction set and the M instruction set extension for multiplication/division operations as per the RISC-V ISA specification.

Other Sub Topics

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Links

• Project Repository
• Project Page
• Department of Computer Engineering
• University of Peradeniya