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RV32IM Pipeline Implementation

Table of Contents

  1. Introduction
  2. Pipeline Datapath
  3. Team
  4. Supervisors
  5. Links


The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWave was used to observe the behavior.

GitHub Repository

Pipeline Datapath

Pipeline Image


  • E/16/069, Damsy De Silve, email
  • E/16/094, Shirly Ekanayake, email
  • E/16/276, Buddhi Perera, email


  • Dr. Isuru Navinna
  • Dr. Mahanama Wickramasinghe