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Control Signals Generated by the Control Unit


IMM_SEL

This control signal is for the immediate value generation unit. In RISC-V ISA, according to the ordering of the immediate value bits there are 7 variants (See Immediate value generation unit for more details).

  • U - Type
  • J - Type
  • S - Type
  • B - Type
  • I - Type signed
  • I - Type containing shift amount
  • I - Type unsigned

The immediate value generation unit will generate these 7 types of immediate values and the IMM_SEL control signal will select the relevant immediate value. The IMM_SEL control signal is a 3-bit signal and the encoding of the bits are as shown in Table 1.

Immediate‌ ‌Type ‌ IMM_SEL[2]‌ IMM_SEL[1]‌ IMM_SEL[0]
U‌ ‌0‌ ‌ 0‌ 0‌ ‌
J‌ ‌0‌ ‌ 0‌ ‌ 1‌ ‌
S‌ ‌0‌ ‌ 1‌ ‌0‌ ‌
B‌ ‌ 0‌ ‌ 1‌ ‌ 1‌ ‌
I_signed‌ ‌1‌ ‌0‌ ‌0‌ ‌
I_shift‌ 1‌ ‌ 0‌ ‌1‌ ‌
I_unsigned‌ ‌ 1‌ ‌ 1‌ ‌ 1‌

OP1_SEL

The input operand 1 of the ALU unit is of 2 values.

  • PC value - For AUIPC, JAL, B - Type instructions
  • DATA1 (value from the register file) - For all the other remaining instructions

This control signal will select between these two values. This is a 1 - bit control signal and the encoding is shown in Table 2.

Operand‌ ‌1‌ ‌Value‌ ‌ OP1_SEL‌ ‌
DATA1‌ ‌ 0‌ ‌
PC‌ ‌ 1‌ ‌

OP2_sel

The input operand 2 of the ALU unit is of 2 values.

  • DATA2 (value from the register file) - For R - Type instructions
  • Immediate value - For all the other remaining instructions

This control signal will select between these two values. This is a 1 - bit control signal and the encoding is shown in Table 3.

Operand‌ ‌2‌ ‌Value‌ ‌OP2_SEL‌ ‌
DATA2‌ ‌ 0‌ ‌
Immediate‌ ‌Value‌ ‌ 1‌ ‌

ALU_OP

This signal will select the relevant ALU operation out of the 18 ALU operations . This is a 5 - bit control signal and the encoding is shown in Table 4.

ALU‌ ‌operation‌ ‌ ALU_OP[4] ‌ ALU_OP[3]‌ ALU_OP[2] ‌ ALU_OP[1] ‌ ALU_OP[0]
ADD‌ ‌ 0‌ ‌ 0‌ ‌ 0‌ ‌ 0‌ 0‌ ‌
SUB‌ ‌ 0‌ ‌ 0‌ 0‌ 1‌ 0‌ ‌
SLL‌ ‌ 0‌ ‌ 0‌ 1‌ 0‌ 0‌ ‌
SLT‌ ‌ 0‌ ‌ 1‌ 0‌ ‌ 0‌ ‌ 0‌ ‌
SLTU‌ ‌ 0‌ ‌1‌ ‌ 1‌ 0‌ 0‌ ‌
XOR‌ ‌ 1‌ ‌ 0‌ 0‌ ‌ 0‌ ‌ 0‌ ‌
SRL‌ ‌ 1‌ ‌ 0‌ ‌ 1‌ ‌ 0‌ ‌ 0‌ ‌
SRA‌ ‌ 1‌ ‌ 0‌ ‌ 1‌ ‌1‌ ‌ 0‌
OR‌ ‌ 1‌ ‌ 1‌ ‌ 0‌ ‌ 0‌ ‌ 0‌ ‌
AND‌ ‌ 1‌ ‌ 1‌ ‌ 1‌ ‌ 0‌ ‌ 0‌
MUL‌ ‌ 0‌ 0‌ ‌ 0‌ ‌ 0‌ ‌ 1‌ ‌
MULH‌ ‌ 0‌ ‌0‌ 1‌ ‌ 0‌ ‌ 1‌ ‌
MULHU‌ ‌ 0‌ 1‌ 0‌ 0‌ ‌ 1‌ ‌
MULHSU‌ ‌ 0‌ ‌1‌ 1‌ ‌ 0‌ ‌ 1‌
DIV‌ ‌ 1‌ ‌ 0‌ ‌ 0‌ ‌ 0‌ ‌ 1‌ ‌
DIVU‌ ‌ 1‌ ‌ 0‌ ‌ 1‌ ‌0‌ ‌ 1‌
REM‌ ‌ 1‌ ‌ 1‌ 0‌ ‌0‌ ‌ 1‌ ‌
REMU‌ ‌ 1‌ ‌ 1‌ ‌ 1‌ ‌0‌ ‌1‌ ‌

BRANCH_JUMP

This control signal will select the type of branching to be considered by the Branching and Jump detection unit. Instructions in RV32IM can be categorized into 8 categories depending on their branching (See Branching and Jump Detection Unit for more details).

  • BEQ - For BEQ instruction
  • BNE - For BNE instruction
  • J - For J - Type instruction
  • BLT - For BLT instruction
  • BGE - For BGE instruction
  • BLTU - For BLTU instruction
  • BGEU - For BGEU instruction
  • NO - For all other remaining instructions

BRANCH_JUMP control signal is a 3 - bit control signal and encoding is shown in Table 5.

Branch‌ ‌Type BRANCH_JUMP[2] BRANCH_JUMP[1] BRANCH_JUMP[0]
BEQ‌ ‌0‌ ‌0‌ ‌0‌ ‌
BNE‌ ‌0‌ ‌0‌ ‌ 1‌ ‌
NO‌ ‌0‌ ‌ 1‌ ‌0‌ ‌
J‌ ‌ 0‌ ‌ 1‌ 1‌ ‌
BLT‌ ‌ 1‌ ‌0‌ ‌ 0‌ ‌
BGE‌ ‌ 1‌ ‌ 0‌ ‌ 1‌ ‌
BLTU‌ ‌1‌ ‌1‌ ‌0‌ ‌
BGEU‌ ‌ 1‌ ‌ 1‌ ‌ 1‌ ‌

READ_WRITE

In‌ ‌RISC-V‌ ‌ISA,‌ ‌there‌ ‌are‌ ‌5‌ ‌types‌ ‌of‌ ‌load‌ ‌instructions‌ ‌and‌ ‌3‌ ‌types‌ ‌of‌ ‌store‌ ‌instructions‌ ‌depending‌ ‌on‌‌ the‌ ‌number‌ ‌of‌ ‌bits‌ ‌loaded/stored.‌ ‌This‌ ‌control‌ ‌signal‌ ‌is‌ ‌sent‌ ‌to‌ ‌the‌ ‌data‌ ‌cache‌ ‌memory‌ ‌and‌ ‌the‌ ‌data‌‌ cache‌ ‌memory‌ ‌will‌ ‌load/store‌ ‌according‌ ‌to‌ ‌the‌ ‌READ_WRITE‌ ‌signal.‌

‌Types‌ ‌of‌ ‌load/store‌ ‌instructions‌‌ are,

  • LB‌ ‌-‌ ‌Load‌ ‌byte‌ ‌(8‌ ‌bits‌ ‌from‌ ‌given‌ ‌address)‌ ‌
  • LH‌ ‌-‌ ‌Load‌ ‌halfword‌ ‌(16‌ ‌bits‌ ‌from‌ ‌given‌ ‌address)‌ ‌
  • LW‌ ‌-‌ ‌Load‌ ‌word‌ ‌(32‌ ‌bits‌ ‌from‌ ‌given‌ ‌address)‌ ‌
  • LBU‌ ‌-‌ ‌Load‌ ‌byte‌ ‌unsigned(8‌ ‌bits‌ ‌from‌ ‌given‌ ‌address)‌ ‌
  • LHU‌ ‌-‌ ‌Load‌ ‌halfword‌ ‌unsigned(16‌ ‌bits‌ ‌from‌ ‌given‌ ‌address)‌ ‌
  • SB‌ ‌-‌ ‌Store‌ ‌byte‌ ‌(least‌ ‌significant‌ ‌8‌ ‌bits‌ ‌from‌ ‌input‌ ‌data)‌ ‌
  • SH‌ ‌-‌ ‌Store‌ ‌halfword‌ ‌(least‌ ‌significant‌ ‌16‌ ‌bits‌ ‌from‌ ‌input‌ ‌data)‌ ‌
  • SW‌ ‌-‌ ‌Store‌ ‌word‌ ‌(32‌ ‌bits‌ ‌from‌ ‌input‌ ‌data)‌ ‌

READ_WRITE‌ ‌control‌ ‌signal‌ ‌is‌ ‌a‌ ‌4‌ ‌bit‌ ‌control‌ ‌signal‌ ‌and‌ ‌the‌ ‌encoding‌ ‌is‌ ‌shown‌ ‌in following table.

Load/Store Type READ_WRITE[3] READ_WRITE[2] READ_WRITE[1] READ_WRITE[0]
No‌ ‌load/store‌ ‌ 0‌ ‌ 0‌ ‌0‌ ‌ 0‌ ‌
LB‌ ‌ 1‌ ‌ 0‌ ‌0‌ ‌0‌ ‌
LH‌ ‌ 1‌ ‌ 0‌ ‌ 0‌ ‌ 1‌ ‌
LW‌ ‌1‌ ‌ 0‌ ‌ 1‌ ‌0‌ ‌
LBU‌ ‌ 1‌ ‌ 1‌ ‌0‌ ‌ 0‌ ‌
LHU‌ ‌ 1‌ ‌1‌ ‌0‌ ‌ 1‌ ‌
SB‌ ‌1‌ ‌0‌ ‌ 1‌ ‌ 1‌ ‌
SH‌ ‌ 1‌ ‌ 1‌ ‌ 1‌ ‌ 0‌ ‌
SW‌ ‌ 1‌ ‌1‌ ‌ 1‌ ‌ 1‌

WB_SEL

There are 4 sources for the write back value to be written to the register file.

  • ALU result - For AUIPC, I - Type and R - Type
  • Data from the data memory - For Load instructions
  • Immediate value - For LUI instruction
  • PC + 4 value - For J - Type instruction

This control signal will select between these 4 sources. The WB_SEL signal is a 2 - bit control signal and the encoding is shown in following table.

Writeback‌ ‌Source‌ ‌WB_SEL[1]‌ WB_SEL[0]‌
ALU‌ ‌result‌ ‌ 0‌ ‌ 0‌
Data‌ ‌from‌ ‌data‌ ‌memory‌ ‌ 0‌ ‌ 1‌
Immediate‌ ‌value‌ ‌ 1‌ ‌ 0‌
PC‌ ‌+‌ ‌4‌ ‌ 1‌ ‌ 1‌

REG_WRITE_EN

This control signal will enable writing to the register file. When REG_WRITE_EN is set, the write back value is written to the register file and when REG_WRITE_EN is cleared, the write back value is not written to the register file.