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Hardware Units
Control Unit
Control Signals Generated by the Control Unit
Control Unit Design
Instructions and the Control Signals
ALU
Register File
Branch and Jump Detection Unit
Immediate Value Generation Unit
Program Counter Register
Multiplexers
Program Counter Incrimeting Adder
Pipeline Register
Memory Hierarchy
Data Cache
Data Memory
Instruction Cache
Instruction Memory
Timing and Simulation Delays
Simulation Delays of Hardware Units
Clock Cycle Period
Hazard Detection and Handling Hazards
Types of Hazards
Handling Data Hazards
Forwarding unit Hardware
Handling Control Hazards
Pipeline Datapath with Forwarding Mechanism
Integrated CPU
Testing
Project Repository on GitHub
Timing and Simulation Delays
Table of contents
Simulation Delays of Hardware Units
Clock Cycle Period